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www.fa irchildsemi.com ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 AN-6902 applying sg6902 to control a ccm pfc and flyback/pwm power supply summary this application note shows a step-by-step design to a 120w/24v power adapter. the equations also can be applied to different output voltages and wattages. features ? interleaved pfc/pwm switching ? green-mode pfc/pwm switching ? no pfc switching at light loads for power saving ? innovative switching char ge multiplier-divider ? low startup and operating current ? innovative switching char ge multiplier-divider ? multi-vector control for improved pfc output transient response ? average-current-mode control for pfc ? programmable two-level pfc output voltage to achieve the best efficiency ? pfc over-voltage and under-voltage protections ? pfc and pwm feedback open-loop protection ? cycle-by-cycle current limiting for pfc/pwm ? slope compensation for pwm ? maximum power limit for pwm ? brownout protection ? over temperature protection ? power-on sequence control and soft-start ? 20-pin sop and ssop packages description sg6902 is designed for power supplies that consist of boost pfc and flyback pwm. it requires few external components to achieve green-m ode operation and versatile protections and compensations. the proprietary interleave switching synchronizes the pfc and pwm stages and reduces switching noise. at light loads, pfc stage is turned o ff to save power and the pwm switching frequency is decreased in response to the load. for pfc stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth pfc loop. the overshoot and undershoot of the pfc voltage are clamped. if the feedback loop is broken, sg6902 shuts off the switching to protect the power supply and its load. for the flyback pwm stage, the synchronized slope compensation ensures the stab ility of the current loop. ?hiccup? operation limits a maximum output power during the overload situations. the difference between members of this family are shown in the table below. parameter sg6902 sg6901a start threshold voltage 16v 12v minimum operating voltage 10v 10v the interval of opfc lags behind opwm at startup 11.5ms 11.5ms pfc on/off o x otp o o soft-start o o
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 2 pin configuration figure 1. pin configuration typical application figure 2. typical application
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 3 block diagram figure 3. block diagram
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 4 pfc section power-on sequence sg6902 is active when the line voltage is higher than the brownout threshold. the pwm stage is switching first, then, following an 11.5ms delay time after fbpwm voltage is higher than a pfc turn-on threshold voltage, the pfc stage is enabled. pfc inductor the switching frequency f s , output power p out , efficiency n , maximum ripple current i, and minimum input voltage v in.min should be defined before determining the inductance of pfc inductor. the following equations are utilized to determine the inductance of the pfc inductor. normally the maximum ripple current is 20% ~ 30% of maximum input current. () ) min ( in out v 3 . 0 / p 2 i = (1) o min . in v 2 v 1 d ? = (2) dt di l v = (3) i fs / d max = 2 v l in.min (4) for a 120w adapter power, = 0.85, v in(min) = 90v ac, f s = 65khz, v o = 250v, i = 0.66a, d = 0.49, l = 0.4mh. pfc capacitor an advantage of using interleaving switching of pfc and pwm stage is to reduce the switching noise. the esr requirement of boost capacitor is relaxed. the boost capacitor value is chosen to remain a hold-up time of output voltage in the event line voltage is removed. () 2 min . o 2 ripple ) normal ( o o v v v ? ? = up - hold pwm out t ) / (p 2 c (5) where v o.min is the minimum output voltage in accordance with the requirement of the specification. for a 120w power supply, the capacitor is determined as: () () f 86 60 20 250 ms 15 85 . 0 / w 120 2 c 2 2 o = ? ? > (6) because the capacitor includes 20% variation, the capacitor 100f is chosen. figure 4. interleaving switching boost rectifier and switch the fast reverse-recovery time of the boost diode is required to reduce the power losses and the emi. a 500v voltage rating is chosen to withstand 400v boosts potential. the average current and peak currents flow through the boost diode and the switch, respectively, and are given by: a 82 . 2 75 8 . 0 / 120 2 i v / p 2 i a 8 . 1 75 8 . 0 / 120 2 2 i v / p 2 2 i peak ) brownout ( rms out peak avg ) brownout ( rms out avg = = = = = = (7) oscillation and green mode the resistor r i connected from the ri to gnd pin programs the switching frequency of sg6902. () () khz k r f i s = 1560 (8) for example, a 24k ? resistor r i results in a 65khz switching frequency. the recommended range for the switching frequency is 33khz ~ 100khz. sg6902 provides an off-time modulation to reduce the switching frequency in light-load and no-load conditions. the feedback voltage of fbpwm pin is taken as reference. when the feedback voltage is lower than about 2.1v, the switching frequency decreases accordingly. most of losses in a switching-mode power supply are proportional to the switching frequency; therefore, the off-time modulation reduces the power consumption of the power supply in light-l oad and no-load conditions. for a typical case of r i = 24k ? , the switching frequency is 65khz at nominal load and decreases to 20khz at light load. the switching signal is disabled if the switching frequency falls below 20khz, wh ich avoids acoustic noise. for stability reasons, a capacito r connecting the ri pin to gnd is not suggested.
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 5 f s 2.1 20khz f bpwm(v) figure 5. switching frequency vs. fb voltage to save power, the pfc stag e is enabled only when the feedback voltage of the fbpwm pin is higher than a threshold voltage v th . the threshold voltage v th is 2.1v to 2.45v at low line voltage input, 1.95v at high line voltage. the threshold voltage v th determines an output power threshold to turn on/off the pfc stage for the power saving. the output power p out can be expressed as: () t l 2 t v p p 2 on in out = (9) ? ? ? ? ? ? ? ? ? ? + + = on sl on s p ) peak ( in fb t t v t r l v 3 v 2 . 1 v (10) where v sl is a synchronized 0.5v ramp. equation 10 shows that, through the feedback loop, the on-time t on changes in response to the change of the switching period t and/or the inductance l p (the primary inductance of the transformer) for providing a same output power. because the feedback voltage v fb controls the on-time t on , a lower v fb causes a narrow on-time t on . changing the switching frequency (the switching period t) and the inductance l p , affects the output power threshold to on/off the pfc stage. i ac signal figure 6 shows that the i ac pin is connected to the input voltage via a resistor. a current i ac is used for pfc multiplier. ac ) peak ( in ) peak ( ac r v i (11) for wide range input: () v 374 2 v 264 v peak in = = (12) the linear range of i ac is 0~360a. a 1.2m resistor is suggested for a wide input range (90v ac ~ 264v ac ). figure 6. linear range line voltage detection (v rms ) figure 6 shows a resistive divider with low-pass filter connected to the vrms pin for line-voltage detection. the v rms input is used for the pfc multiplier and brownout protection. for a sine wave input voltage, the voltage on the vrms pin is directly proportional to input voltage. to achieve the brownout protection, the pfc stage is disabled after a 195ms delay once the v rms voltage drops below 0.8v. the pwm stage is protected through the open-loop detection on the fbpwm pin when the output voltage of the pfc stage is too low. after that, sg6902 turns off. when v rms voltage is higher than 0.98v, the sg6902 restarts in accordance with power-on sequence of pfc and pwm stages. for example, a brownout protection is set as 75v ac . the r rms and r i can be determined as: 2 2 v v in ) mean ( in = (13) 2 2 v r 1 r 1 r v in rms rms + = (14) the threshold of v rms = 0.8v. if r rms = 4.8m and v in = 75v ac , the value of r1 is 56.8k .
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 6 pfc operation figure 7. current output the current source output from the switching charge multiplier/divider can be expressed as: ) a ( v v i k i 2 rms ea ac mo = (15) according to figure 7, the current output from imp pin, i mp , is the summation of i mo and i mr1 . the resistor r 2 is equipped as same as r 3 . the constant current source i mr1 is identical with i mr2 . they are used to bias (pull high) the operating point of the imp and ipfc pins since the voltage across r s goes negative with respect to ground. through the differential amplification of the signal across r s , a better noise immunity is acjoeved. the output of i ea compared with an internal sawtooth generates a switching signal for pfc. through the feedback loop of the average current control mode, the input current i s is proportional to i mo : s s 2 mo r i r i = (16) according to this equation, the minimum value of r 2 and maximum value of r s can be determined. the i mo should be estimated under its specified maximum value. a concern in determining the value of the sense resistor r s includes low-resistance r s reduces the power consumption, but high-resistance r s provides high resolution to achieve low input current thd (total harmonic distortion). using a current transformer (ct) instead of r s improves the efficiency for high-power converters.for a 120w adapter, the power consumption of r s = 0.36 is: w 885 . 0 36 . 0 90 85 . 0 / w 120 p 2 rs = ? ? ? ? ? ? = (17) r 2 and r 3 can be determined as (the brownout threshold is 75v): 308 0 3.3k 2.83 0.36 i r i r i 2.83a 2 75v 120w/0.8 mo 2 max s mo max = = = = = i (18) the results show that r s , r 2 , and r 3 values are fit for providing 120w output. cycle-by-cycle current limiting sg6902 provides cycle-by-cycle current limiting for both pfc and pwm stages. figure 8 shows the peak current limit for the pfc stage. the switching signal of pfc stage is turned off imme diately once the voltage on isense pin goes below the threshold voltage v pk . the voltage of v rms determines the threshold voltage v pk . the correlation of the threshold voltage v pk and vrms is shown in figure 8. the amplitude of the constant current i p shown in figure 8 is determined by a reference current i t , in accordance w ith the following equation as: i t p r v 2 . 1 2 i 2 i = = (19) therefore, the peak current of the i s can be expressed as: ( ) s p p peak _ s r v 2 . 0 r i i ? = (20) figure 8. current limit multi-vector error amplifier to achieve good power factor, the voltage for v rms and v ea should be kept as dc-v alue according to equation 14. in other words, a low-pass rc filtering for v rms and a narrow bandwidth (lower than the line frequency) of pfc voltage loop are suggested to achieve better input current shaping. the trans-conductance error amplifier has output impedance r o (>90k ). a capacitor c ea (1f ~ 10f) is suggested to connect from the output of the error amplifier to ground (figure 9). a dominant pole f 1 of the pfc voltage loop is shown as: ea o 1 c r 2 1 f = (21) the average total input power can be expressed as: ()() ea 2 rms ea ac in rms 2 rms ea ac rms mo rms rms in rms in in v v v r v v v v i v i v i v p = (22)
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 7 figure 9. multi-vector error amplifier equation 22 shows the output of the voltage error amplifier, v ea , controls the total input power and the power delivered to the load. although the pfc stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of pfc output voltage. figure 10 shows the block diagram of the multi-vector error amplifier. when the variation of the feedback voltage (fbpfc) exceeds 5% of the reference voltage (3v), the trans-conductance error amplifier programs its output current to speed up the loop response. if r a is open circuit, sg6902 is turned off immediately to prevent over-voltage on the output capacitor. two-level pfc output voltage for universal input (90v ac ~ 264v ac ), the output voltage of pfc is usually designed to 250v at low line and 400v at high line. this improves efficiency of the power converter for low-line input. the range pin (open- drain) is used for the two-level output voltage setting. figure 10 shows the range output that programs the pfc output voltage. the range output is shorted to ground when the v rms voltage exceeds 1.95v. it is a high-impedance output (open) whenever the v rms voltage drops below 1.6v. the output voltages can be determined using below equations: v 3 r r r v open range b b a o + = ? = (23) () () v 3 r // r r // r r v gnd range c b c b a o + = ? = (24) determine the resistor divider ratio r a /r b : 1 3 v r r o b a ? = (25) 33 . 82 1 3 250 r r b a = ? = (26) assume r a = 3m ? , r b = 36.5k ? , and r c = 60k ? . refer to figure 10 . at high line input, maximum output voltage is: v 420 1 r // r r 15 . 3 v c b a ) max ( o = ? ? ? ? ? ? ? ? + = = (27) another circuit provides further over-voltage protection to inhibit the pfc switching once the feedback voltage exceeds the 3.25v the output voltage is clamped at: v 433 1 r // r r 25 . 3 v c b a ) ovp ( o = ? ? ? ? ? ? ? ? + = (28) figure 10. feedback voltage of pfc pwm section soft-starting the pwm stage the soft-start pin controls the rising time of the output voltage and prevents the overshoot during power on. the soft-start capacitor value fo r the soft-start period t ss is given by: oz ss ss ss v i t c = (29) where v oz is the zero-duty threshold of fbpwm voltage. v o r b r c r a vea fbpfc range 3v + sg69xx (pfc)
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 8 leading-edge blanking (leb) a voltage signal develops on the current-sense resistor r s represents the switching current of mosfet. each time the mosfet turns on, a spike, caused by the diode reverse recovery time and by the parasitic capacitances of the mosfet, appears on the sensed signal. the sg6902 has a build-in leading-edge blanking time of about 350ns to avoid premature termination of mosfet by the spike. only a small-value rc filter (e.g. 100 + 47pf) is required between the ipwm pin and r s to prevent negative spike into the ipwm pin. a non-inductive resistor for the r s is recommended. figure 11. turn-on spike flyback pwm and slope compensation as shown in figure 12, peak-current-mode control is utilized for flyback pwm. the sg6902 inserts a synchronized 0.5v ramp at the beginning of each switching cycle. this built-in slope compensation reduces the current loop gain and ensures stable operation for current-mode operation. when the ipwm voltage, across the sense resistor, reaches the threshold voltage, 0.65v or 0.7v selected by range, the opwm turns off after a small propagation delay, t pd-pwm . this propagation delay introduces an additional current proportional to t pd-pwm ?v pfc /lp, where v pfc is the output voltage of pfc and lp is the magnetized inductance of flyback transformer. since the propagation delay is nearly constant, higher v pfc results in a larger additional current and the output power limit is higher than that of the low v pfc . to compensate for this variation, the peak current threshold is modulated by the range output. when range is shorted to gnd, the pfc output voltage is higher and the corresponding threshold is 0.65v. when range is opened, the pfc output voltage is lower and the corresponding threshold is 0.7v. increasing the inductance of transformer improves this phenomenon. figure 12. current limit and slope compensation output driver of opfc and opwm sg6902?s opfc and opwm is fast totem-pole gate driver that is able to directly drive external mosfet. an internal zener diode clamps the driver voltage under 18v to protect mosfet from over-voltage damage. on/off driver vdd 18v sg6841 gate figure 13. gate drive over-current protection (ocp) and short- circuit protection (scp) ocp and scp are based on detection of feedback signal on fbpwm pin. shown in figure 14, if over-current or short-circuit occurs, fbpwm is pulled high through the feedback loop. if the fb voltage is higher than 4.5v for longer than 56ms debounce time, sg6902 is turned off. once v dd is lower than the turn-off threshold voltage, such as 10v, sg6902 is uvlo (under-voltage lockout) shut down. by the startup resistor, v dd is charged (up to the turn-on threshold voltage 16v) until sg6902 is enabled again. if the overloading condition still exists, the protection takes place repeatedly . this prevents the power supply from being overheated in overloading condition . the 650ms time-out signal prevents sg6902 from being latched off when the input voltage is fast on/off. gate sense sg6841 blanking circuit
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 9 figure 14. over-current protecti on or short-circuit protection over-temperature protection (otp) sg6902 provides an otp pin for over-temperature protection. a constant current is output from this pin. if ri is equal to 24k ? , the magnitude of the constant current is 100a. an external ntc thermistor must be connected from this pin to ground as shown in figure 15. when the otp voltage drops below 1.2v, sg6902 is disabled until otp voltage exceeds 1.4v. figure 15. over-temperature protection flyback transformer design the turn ratio n = np/ns, is an important parameter for a flyback power converter. it affects the maximum duty of the switching signal when the input voltage is in minimum value. it also influences the voltage stresses of the mosfet and the secondary rectifier. refer to equations 30 and 31. if n increases, the voltage stress of the mosfet increas es; however, the voltage stress of the secondary rectifier decreases accordingly. () f o max . in max . ds v v n v v + + = (30) o ma . in max . ak v n x v v + = (31) where v f is the forward voltage of output diode and v in.max = 400v. referring to the maximum duty cycle and minimum input voltage at full load, the transformer inductance can be calculated as: ( ) () f o min . in f o max v v n v v v n d + + + = (32) () r s out 2 max max in p b f p 2 d v l = (33) where b r is how much percentage of the output power is into ccm in low line input voltage. normally, the b r is set as 30% ~ 50%. v in.min = 250v. av i s q i p k i p i max d max 1- d figure 16. primary current waveform figure 16 shows the primary current waveform. once the inductor l p is determined, the primary peak current i pk and average current i av , at the full load and low line input voltage, can be expressed as: max max . in o av d v p i = (34) s max p max . in p t d l v i = (35)
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 10 av p pk i 2 i i + = (36) p pk sq i i i ? = (37) from faraday?s law, the turns of primary side can be expressed as: 8 e max pk p p 10 a b i l n = (38) the turns of auxiliary winding can be expressed as: ()() max max . in max fa dd p aux d v d 1 v v n n ? + = (39) where v dd is set to around 12v and v fa is the forward voltage of v dd rectifier diode. transformer winding structure the auxiliary winding of the transformer is developed to provide a power source (v dd voltage) to the control circuit. to produce a regulated v dd voltage, the reflected voltage of the auxiliary winding is designed to correlate to the output voltage of secondary winding. a switching voltage spike, caused by the leakage inductance of the primary winding, would be coupled to the auxiliary winding to increase the v dd voltage in response to the increase of the load. when the v dd voltage is increased higher than the voltage of the over-voltage protection 24.5v, the control circuit turns off the pwm and pfc stages to protect the power supply. therefore, the transformer windings should prevent the auxiliary winding from primary winding interference. figure 17 shows a transformer winding structure, including primary winding (np1), copper layer (shield), secondary winding (ns), auxiliary winding (aux), copper layer (shield), and primary winding (np2). because the auxiliary windi ng is between secondary winding and shield windings, it can alleviate the variation of v dd voltage and avoid the v dd voltage reaching the over-voltage threshold of 24.5v for normal operation. figure 17. winding structure lab note before rework or solder/desolder on the power supply, discharge primary capacitors by external bleeding resistor. otherwise, the pwm ic may be destroyed by external high voltage during solder/desolder. this device is sensitive to esd discharge. to improve production yield, the production line should be esd protected according to ansi esd s1.1, esd s1.4, esd s7.1, esd stm 12.1, and eos/esd s6.1
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 11 printed circuit board layout note that sg6902 has two ground pins. good high- frequency or rf layout practices should be followed. avoid long pcb traces and component leads. locate decoupling capacitors near the sg6902. a resistor (5 ~ 20 ) is recommended, connected in series from the opfc and opwm to the gate of the mosfet. isolating the interference between the pfc and pwm stages is also important. figure 18 shows an example of the pcb layout. the ground trace connected from the agnd pin of sg6902 to the decoupling capacitor, which should be low impedance and as short as possible. the ground trace 1 provides a signal ground. it should be connected directly to the decoupling capacitor v dd and/or to the agnd pin of the sg6902. the ground trace 2 shows that the agnd pins should connect to the pfc output capacitor c o independently. the ground trace 3 is independently tied from the pgnd to the pfc output capacitor c o . the ground in the output capacitor c o is the major ground reference for power switching. to provide a good ground reference and reduce the switching noise of both the pfc and pwm stages, the ground traces 6 and 7 should be located very near and be low impedance. the ipfc pin is connected directly to r s through r 3 to improve noise immunity (beware that it may incorrectly be connected to the ground trace 2). the imp and isense pins should also be connected directly via the resistors r 2 and r p to another terminal of r s . due to the ground trace 4 and 5 is pfc and pwm stages current loop, which should be as short as possible. figure 18. pcb layout
AN-6902 application note ? 2007 fairchild semiconductor corporation www.fairchildsemi.com rev. 1.2.1 ? 5/1/08 12 related datasheets sg6902 ? green mode pfc / flyback pwm controller sg6901a ? green mode pfc / flyback pwm controller disclaimer fairchild semiconductor reserves the right to make changes without further notice to any products herein to improve reliability, function, or design. fa irchild does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights, nor the rights of others. life support policy fairchild?s products are not authorized for use as criti cal components in life support devices or systems without the express written approval of the preside nt of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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